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OPTIMIZATION OF ALGORITHMS AND DATA STRUCTURES FOR REGULAR EXPRESSION MATCHING USING FPGA TECHNOLOGY
Kaštil, Jan ; Plíva, Zdeněk (oponent) ; Vlček, Karel (oponent) ; Kotásek, Zdeněk (vedoucí práce)
This thesis deals with fast regular expression matching using FPGA. Regular expression matching in high speed computer networks is computationally intensive operation used mostly in the field of the computer network security and in the field of monitoring of the network traffic. Current solutions do not achieve throughput required by modern networks with respect to all requirements placed on the matching unit. Innovative hardware architectures implemented in FPGA or ASIC have the highest throughput. This thesis describes two new architectures suitable for the FPGA and ASIC implementation. The basic idea of these architectures is to use perfect hash function to implement transitional function of deterministic finite automaton. Also, architecture that allows the user to introduce small probability of errors into the matching process in order to reduce memory requirement of the matching unit was introduced. The thesis contains analysis of the effect of these errors to overall reliability of the system and compares it to the reliability of currently used approach. The measurement of properties of regular expressions used in analysis of the traffic in modern computer networks was performed in the thesis. The analysis implies that most of the used regular expressions are suitable for the implementation by proposed architectures. To guarantee high throughput of the matching unit new algorithms for alphabet transformation is proposed. The algorithm allows to transform the automaton to accept several input characters per one transition. The main advantage of the proposed algorithm over currently used solutions is that it does not have any limitation over the number of characters that are accepted at once. Implemented architectures were compared with the current state of the art algorithm and 200MB memory reduction was achieve
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Srovnání implementačních strategií DFA
Balgar, Marek ; Šimek, Václav (oponent) ; Kaštil, Jan (vedoucí práce)
Tato bakalářská práce podrobně popisuje výběr metod pro uložení automatu na FPGA a následnou implementaci. Byly vybrány metody bit-split, compress metoda a hashovací tabulka. Dále jsou zde porovnávány jednotlivé paměti, které automaty v reprezentaci jednotlivých metod zaberou. Jsou zde prováděny různé testy s velkou škálou vzorků. Z výsledků jsou zde pak zhodnoceny výhody a nevýhody jednotlivých metod, ale hlavně je zde obsaženo rozhodnutí, která metoda je nejvýhodnější pro uložení automatu na FPGA.
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OPTIMIZATION OF ALGORITHMS AND DATA STRUCTURES FOR REGULAR EXPRESSION MATCHING USING FPGA TECHNOLOGY
Kaštil, Jan ; Plíva, Zdeněk (oponent) ; Vlček, Karel (oponent) ; Kotásek, Zdeněk (vedoucí práce)
This thesis deals with fast regular expression matching using FPGA. Regular expression matching in high speed computer networks is computationally intensive operation used mostly in the field of the computer network security and in the field of monitoring of the network traffic. Current solutions do not achieve throughput required by modern networks with respect to all requirements placed on the matching unit. Innovative hardware architectures implemented in FPGA or ASIC have the highest throughput. This thesis describes two new architectures suitable for the FPGA and ASIC implementation. The basic idea of these architectures is to use perfect hash function to implement transitional function of deterministic finite automaton. Also, architecture that allows the user to introduce small probability of errors into the matching process in order to reduce memory requirement of the matching unit was introduced. The thesis contains analysis of the effect of these errors to overall reliability of the system and compares it to the reliability of currently used approach. The measurement of properties of regular expressions used in analysis of the traffic in modern computer networks was performed in the thesis. The analysis implies that most of the used regular expressions are suitable for the implementation by proposed architectures. To guarantee high throughput of the matching unit new algorithms for alphabet transformation is proposed. The algorithm allows to transform the automaton to accept several input characters per one transition. The main advantage of the proposed algorithm over currently used solutions is that it does not have any limitation over the number of characters that are accepted at once. Implemented architectures were compared with the current state of the art algorithm and 200MB memory reduction was achieve
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Srovnání implementačních strategií DFA
Balgar, Marek ; Šimek, Václav (oponent) ; Kaštil, Jan (vedoucí práce)
Tato bakalářská práce podrobně popisuje výběr metod pro uložení automatu na FPGA a následnou implementaci. Byly vybrány metody bit-split, compress metoda a hashovací tabulka. Dále jsou zde porovnávány jednotlivé paměti, které automaty v reprezentaci jednotlivých metod zaberou. Jsou zde prováděny různé testy s velkou škálou vzorků. Z výsledků jsou zde pak zhodnoceny výhody a nevýhody jednotlivých metod, ale hlavně je zde obsaženo rozhodnutí, která metoda je nejvýhodnější pro uložení automatu na FPGA.
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